The K32W148 wireless MCU simplifies development of IoT devices with modular security and connectivity subsystems, allowing developers to focus on their innovation. With its integrated RF subsystem and a total memory footprint between the application core and the networking subsystem of 1.25 MB Flash and 216 KB RAM, the K32W148 enables seamless integration of Matter, Thread, Zigbee and Bluetooth Low Energy.
The K32W148 Arm® Cortex®-M33 main core, with 1 MB on-board flash and 128 KB SRAM, has enough room and flexibility for complex applications and over-the-air (OTA) upgrade capability without external memory. It also includes a rich set of MCU digital and analog peripherals and multiple serial communication interfaces for embedded connected applications.
Supporting the application core are a dedicated radio subsystem and an isolated EdgeLock® secure enclave. The radio subsystem, with its 256 kB Flash and 88 kB SRAM, offloads low-level radio operations from the application core, freeing resources for the main application, providing robust wireless performance and optimizing system level current draw. It also supports hardware accelerated Dual-PAN which enables bridging use cases for Thread and Zigbee with faster and more reliable time-slicing.
The EdgeLock secure enclave enables advanced security features such as key generation and storage, secure lifecycle management, secure boot and cryptographic acceleration in a protected execution environment. The K32W148 is also supported by NXP’s EdgeLock® 2GO service which can install keys and certificates securely into the end devices and maintain the credentials throughout their life cycle. This service is authorized by the Connectivity Standards Alliance to serve as a Product Attestation Authority for Matter device attestation certificates streamlining the process for device manufacturers to develop and deploy a full Matter device.
Key Features
Application Core
- Up to 96 MHz Arm Cortex-M33 core
- 1 MB program Flash with ECC
- 128 kB SRAM
- Nested Vectored Interrupt Controller (NVIC)
- Wake-Up Interrupt Controller (WIC)
Radio Core
- Dedicated CM3 core
- Secure 256 kB Flash for authenticated NXP 15.4 and Bluetooth Low Energy controller stack firmware
- 88 kB dedicated SRAM
- IEEE 802.15.4–2015 compliant radio
- 101 dBm 250 kbps receive sensitivity
- Improved enhanced ACK timing support in the 802.15.4 hardware
- Dual PAN support
- 2.4 GHz Bluetooth Low Energy Version 5.3 upgradeable radio supporting up to 24 simultaneous hardware connections in any central/peripheral combination
- –106 dBm 125 kbps Long Range Receive Sensitivity
- –102 dBm 500 kbps Long Range Receive Sensitivity
- –97.5 dBm 1 Mbps Receive Sensitivity
- –95 dBm 2 Mbps Receiver Sensitivity
- Programmable Transmit Output Power up to +10 dBm
- Data Rates: 125 kbps, 500 kbps, 1 Mbps, and 2 Mbps
- Modulation Types: 2 Level FSK, GFSK, MSK, GMSK
- On-chip balun with single ended bidirectional RF port
EdgeLock Secure Enclave
- Secure Boot and Debug
- Symmetric Key Encryption – AES-128/192/256 and ECB, CBC, CTR, GCM, CMAC and CCM Modes
- Asymmetric Key Encryption – ECC NIST P–192/224/256/384/521, Curve25519
- Key Exchange algorithms – ECDH(E), SPAKE2+, JPAKE
- Secure Key Generation, Storage and Management
- Flash access protection and optional encryption on-the-fly decryption using a PRINCE XEX block cipher mode
Low Power Consumption
- Transceiver current (DC-DC buck mode, 3.3 V supply)
- Typical RX: 4.7 mA
- Typical TX at 0 dBm: 4.6 mA and 18.7 mA at 10 dBm
- Multiple power-down modes supporting currents as low as 300 nA
- Ultra-low leakage Smart Power Switch with less than 100 nA sleep current with exit from internal timer or GPIO.
Human Machine Interface
- 29 GPIO (48HVQFN)
System Peripherals
- DC/DC converter supporting buck and bypass operating modes
- Asynchronous DMA controller with per channel access permissions (secure/non-secure)
- Wake-Up unit for power-down modes
Analog Modules
- 16-bit single ended SAR analog-to-digital converter (ADC) up to 2 Msps
- Two high-speed analog comparators (CMP) with 8-bit digital-to-analog converter (DAC)
- 1.0 V to 2.1 V Voltage Reference (Vref)
- Nested Vectored Interrupt Controller (NVIC)
- Wake-Up Interrupt Controller (WIC)
Timers
- Two 6-channel 32-bit timers (TPM) with PWM capability and DMA support
- Two 32-bit low-power timers (LPTMR) or pulse counters with compare features
- 4-channel 32-bit low-power periodic interrupt timer (LPIT) with DMA support
- One 56-bit timestamp timer
- 32-bit seconds real time counter (RTC) with 32-bit alarm and independent power supply
- Signal frequency analyzer (SFA) provides facilities for measurement of clock period/frequency as well as time between triggers
Communication Interfaces
- Two Low Power UART (LPUART) modules
- Two Low Power SPI modules and one MIPI-I3C module
- Two Low Power I2C (LPI2C) modules supporting the System Management Bus (SMBus) Specification, version 2
- One programmable FlexIO module supporting emulation of UART, I2C, SPI, Camera IF, LCD RGB, PWM/ Waveform generation
Packaging
- 7 x 7 mm 48HVQFN with “Wettable” flanks
